Head of Edge AI Optimization
- Hanoi/HCMC
- Fulltime
Position details
Department | Edge AI Optimization Department, Foundation AI Division, VinRobotics |
Reports to | Director, Foundation AI Division |
Location | Hanoi or Ho Chi Minh City |
Purpose of the role
Lead the Edge AI Optimization Department in taking Physical AI models (VLA, world models, RL policies) from research to real robots: running in real time, reliably and energy-efficiently on low-cost edge hardware. The role owns the full optimization and deployment toolchain (VLAOpt), from model compression to inference runtime and integration on VinRobotics humanoid platforms.
Key responsibilities
1. Technical strategy: build and execute the edge optimization and deployment roadmap for the robot platforms; work with the Reinforcement Learning and Robot Foundation AI departments so new models are deployable by design.
2. Runtime and toolchain: lead development of the inference runtimes (vla.cpp, vla.simd) and hardware backends (CUDA/TensorRT, Qualcomm Hexagon NPU, Intel OpenVINO, CPU SIMD); productize the VLAOpt toolchain.
3. Model compression: low-bit quantization (FoldQuantVLA), pruning, distillation and sub-1B-parameter VLAs; balance latency, accuracy and BOM cost.
4. Field deployment: meet latency and reliability targets for factory use cases; work with the EE team to benchmark SoCs/SOMs and recommend hardware choices.
5. Partners and ecosystem: technical point of contact with NVIDIA, Qualcomm and Intel on model support, dev kits and porting; maintain open-source releases (GitHub, Hugging Face), publications and patents.
6. Team leadership: hire to headcount, run the KPI process, and mentor engineers and talent-program members (interns, Young Engineers, Residents).
Requirements
• MSc or PhD in Computer Science, Computer Engineering, Electronics or a related field.
• 5+ years optimizing and deploying deep learning models on edge devices or in production, including 2+ years leading an engineering team.
• Strong modern C++ and Python; deep understanding of hardware architecture (GPU, NPU, SIMD NEON/AVX, memory hierarchy).
• Hands-on experience with at least two of: TensorRT, ONNX Runtime, OpenVINO, Qualcomm QNN, TVM, ggml/llama.cpp, ExecuTorch.
• Solid command of quantization (PTQ, QAT, INT8/INT4), pruning, distillation and transformer inference optimization (KV cache, kernel fusion, batching).
• Professional working English for direct collaboration with international partners.
Preferred
• Has deployed VLAs, VLMs or LLMs on robots or embedded devices; understands diffusion/flow-matching action heads.
• CUDA or NPU kernel development; experience with real-time systems and ROS 2.
• Publications at top venues (CoRL, ICRA, RSS, NeurIPS, MLSys) or impactful open-source contributions.
• Experience evaluating hardware and optimizing BOM cost for commercial products.
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